4-bit Arithmetic Logic Unit (ALU) lab report SIMULATION

The project details the step-by-step modular design, software simulation, and hardware implementation of an ALU capable of performing 16 unique arithmetic, logic, and shifting micro-operations.

Document Structure & Key Contents

• System Overview: An introductory breakdown of how the 4-bit ALU utilizes control words (\(S_3\text{–}S_0\)) to route operations between an Arithmetic Circuit (AC) and a Logic/Shifting Circuit (LSC).

• Modular Sub-components: Schematic design explanations and compilation metrics for the individual building blocks, including:

• 4-bit Register: Built using D-flip-flops with active-low clear signals.

• Logic and Shift Circuit (LSC): Implemented using \(8\times1\) multiplexers for bitwise AND, OR, XOR, and logical shifts.

• Arithmetic Circuit (AC): Utilizes \(4\times1\) multiplexers combined with a structural 4-bit full adder.

• Status Indicator Register: Tracks performance flags by calculating boolean logic for Carry (\(Cy\)), Sign (\(S\)), Zero (\(Z\)), and Overflow (\(V\)).

• Software Verification: Digital implementation data from Quartus II software, including macrocell/pin usage distribution graphs and timing analyzer vector waveforms.

• Physical Hardware Implementation: Live validation photographs and truth tables mapping operations executed on an EMP7128SC PLD microchip seated on an Altera UP2 development board.

• Handwritten Prelab Attachments: Comprehensive engineering drafts detailing truth tables, logic gate networks, and full component wiring layouts.